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NCP4200 Programmable Multi-Phase Synchronous Buck Converter with PMBus
The NCP4200 is an integrated power control IC with a PMBus interface. It combines a highly efficient, multi-phase, synchronous buck switching regulator controller with a PMBus interface, which enables digital programming of key system parameters to optimize system performance and provide feedback to the system. It uses an internal 8-bit DAC to read a Voltage Identification (VID) code directly from the processor, which is used to set the output voltage between 0.375 V and 1.6 V. This device uses a multi-mode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The NCP4200 can be programmed to provide 2-, 3-, or 4-phase operation, allowing for the construction of up to four complementary buck-switching stages. The NCP4200 supports PSI, which is a Power Save Mode. The NCP4200 includes a PMBus interface which can be used to program system set points such as voltage offset, load-line and phase balance and output voltage. Key system performance data, such as CPU current, CPU voltage, and power and fault conditions can also be read back over the PMBus from the NCP4200. The NCP4200 is specified over the extended commercial temperature range of 0C to +85C and is available in a 40 Lead QFN package.
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QFN40 6x6 CASE 488AR 1 40
MARKING DIAGRAM
NCP4200 AWLYYWWG
A WL YYWW G
= Assembly Location = Wafer Lot = Date Code = Pb-Free Package
PIN ASSIGNMENT
PWRGD PSI VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VCC3 ALERT FAULT SDA SCL EN GND IMON IREF RT
1 2 3 4 5 6 7 8 9 10 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
* Selectable 2-, 3-, or 4-Phase Operation at Up to 1.5 MHz per Phase * PMBus Interface - Enables Digital Programmability of Set Points * Logic-Level PWM Outputs for Interface to External High Power * * * * * *
Drivers Fast-Enhanced PWM for Excellent Load Transient Performance Active Current Balancing Between All Output Phases Built-In Power-Good/Crowbar Blanking Supports On-The-Fly (OTF) VID Code Changes Digitally Programmable 0.375 V to 1.6 V Output Supports Both VR11 and VR11.1 Specifications Programmable Short-Circuit Protection with Programmable Latchoff Delay Supports PSI - Power Saving Mode During Light Loads and Read-back of Monitored Values
PIN 1 INDICATOR
NCP4200
TOP VIEW
VCC PWM1 PWM2 PWM3 PWM4 SW1 SW2 SW3 SW4 OD1
11 12 13
14 15 16 17
Applications
ORDERING INFORMATION
Device* NCP4200MNR2G Package QFN40 Shipping 2500/Tape & Reel
* Desktop PC Power Supplies for VRM Modules
*The "G' suffix indicates Pb-Free package. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2009
September, 2009 - Rev. 0
1
RAMPADJ TRDET FBRTN COMP FB CSREF CSSUM CSCOMP ILIMITFS ODN
Publication Order Number: NCP4200/D
18 19 20
NCP4200
SCL SDA
5 4
RT
10
RAMPADJ
11
VCC
30
VCC3
1
ALERT 2 FAULT 3
COMPARATOR
LIMIT REGISTERS
PMBUS
SHUNT REGULATOR
3.3V REGULATOR
20 39
ODN PSI OD1
STATUS REGISTERS GND 7 EN 6 850mV
- +
UVLO SHUTDOWN
DIGITAL CONFIG & VALUE CONTROL REGISTERS
OSCILLATOR SET RESET
+ -
21
EN
29
PWM1
CMP
RESET
ADC CURRENT BALANCING CIRCUIT CONTROL
+ -
CMP
RESET
2 / 3 / 4-PHASE DRIVER LOGIC
28
PWM2
+ -
CMP
RESET
27
PWM3
+
Overvoltage Threshold CSREF
- - +
CMP
RESET
26
PWM4
Undervoltage Threshold
+ -
CROWBAR
CURRENT LIMIT
25 24 23
SW1 SW2 SW3 SW4
PWRGD 40
DELAY
22
CONTROL ILIMITFS 19
+
18 16 17
P CSCOM CSREF CSSUM IMON
IREF 9 COM 14
+
CONTROL
15
TRDET 12
Voltage Threshold
NCP4200
CONTROL
+ -
+ -
PRECISION REFERENCE
VID DAC
BOOT VOLTAGE & SOFT START CONTROL
13
38
37
36
35
34
33
32
31
FBRTN
VID0 VID1 VID2 VID3
VID4
VID5 VID6 VID7
Figure 1. Simplified Block Diagram
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2
-
CURRENT MEASUREMENT AND LIMIT
8
FB
- + -
2.2 18nF
Vin 12V
4.7uF
ADP3121 10nF
1
150 nH
2
BST DRVH 8 IN SW 7 3 OD PGND 6 4 VCC DRVL 5 4.7uF 2.2 18nF 4.7uF 10
Vcc Core
Vcc Core (RTN) Vcc Sense Vss Sense
ADP3121 10nF
1 2
BST DRVH 8 IN SW 7 3 OD PGND 6 4 VCC DRVL 5 4.7uF 2.2 18nF
150 nH
10
PSI
POWER GOOD
4.7uF
ADP3121 10nF
1 2
NCP4200
4.7uF
RAMPADJ TRDET FBRTN COMP FB CSREF CSSUM CSCOMP ILIMFS
220k
ODN
Figure 2. Application Circuit
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PWRGD PSI VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VCC3 ALERT FAULT SDA SCL
3 NCP4200
SW1 SW2 SW3 SW4 OD1 VCC PWM1 PWM2 PWM3 PWM4
150 nH
ALERT FAULT
BST DRVH 8 IN SW 7 3 OD PGND 6 4 VCC DRVL 5 4.7uF 2.2 18nF 1k 1k 1k 1k
PMBus Interface 1nF EN GND IMON IREF RT
10
4.99k
121k
4.7uF
ADP3121 10nF
1
150 nH
2
348k
BST DRVH 8 IN SW 7 3 OD PGND 6 4 VCC DRVL 5 4.7uF
10
NCP4200
ABSOLUTE MAXIMUM RATINGS
Parameter Input Voltage Range (Note 1) FBRTN PWM2 to PWM4, RAMPADJ SW1 to SW4 SW1 to SW4 (< 200 ns) All Other Inputs and Outputs Storage Temperature Range Operating Ambient Temperature Range ESD Capability, Human Body Model (Note 2) ESD Capability, Machine Body Model (Note 2) Lead Temperature Soldering Re-flow (SMD Styles Only, Pb-Free Versions (Note 3) ESDHBM ESDMM TSLD TSTG Symbol VIN VFBRTN Value -0.3 to 6.0 -0.3 to 0.3 -0.3 to VIN +0.3 -5 to +25 -10 to +25 -0.3 to VIN + 0.3 -65 to +150 -10 to 100 2 100 260 Unit V V V V V V C C kV V C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Refer to Electrical Characteristics and Application Information for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC-Q100-002 (EIA/JESD22-A114) ESD Machine Model tested per AEC-Q100-003 (EIA/JESD22-A115) Latchup Current Maximum Rating: 150 mA per JEDEC standard: JESD78 3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
THERMAL CHARACTERISTICS
Parameter Thermal Characteristics; QFN, 6mm x 6mm (Note 1) Thermal Resistance, Junction-to-Air (Note 4) 4. Values based on copper area of 645 mm2 (or 1 in2) Symbol RqJA Value 27 Unit C/W
of 1 oz copper thickness and FR4 PCB substrate.
OPERATING RANGES (Note 1)
Parameter Input Voltage (Note 5) Output Voltage (Adjustable Version Only) Ambient Temperature Symbol VIN VOUT TA Min 1.7 0.375 0 Max 24 1.8 85 Unit V V C
5. Minimum VIN = 1.7 V or (VOUT + VDO), whichever is higher. Maximum Limit for VOUT = VOUT(NOM) - 10%.
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NCP4200
PIN FUNCTION DESCRIPTIONS
Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic VCC3 ALERT FAULT SDA SCL EN GND IMON IREF RT RAMPADJ TRDET FBRTN COMP FB CSREF Description 3.3 V Power Supply Output. A capacitor from this pin to ground provided decoupling for the interval 3.3 V LDO. ALERT Output. Open drain output that asserts low when the VR exceeds a programmable limit. FAULT Output. Open drain output that asserts low when a fault has occurred. The fault can be due to VR or current limit, crowbar, or undervoltage. The trip points are loaded into registers. Digital Input/Output. PMBus serial data bidirectional pin. Requires PMBus pullup. Digital Input. PMBus serial bus clock open drain input. Requires PMBus pullup. Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low. Ground. All internal biasing and the logic output signals of the device are referenced to this ground. Analog Filter Output. A capacitor from this pin to ground sets the default current monitor filter frequency. The frequency can be modified using the serial interface. Current Reference Input. An external resistor from this pin to ground sets the reference current for IFB, IILIMITFS and ITH(X). Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device. PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp. Transient Detect. Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage. Error Amplifier Output and Compensation Point. Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between this pin and the output voltage sets the no load offset point. Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense amplifier and the power-good and crowbar functions. This pin should be connected to the common point of the output inductors. Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor currents together to measure the total output current. Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determines the gain of the current sense amplifier and the positioning loop response time. Current Sense and Limit Scaling Pin. An external resistor from this pin to CSCOMP sets the internal current sensing signal for current limit and IMON. This value can be overwritten using the PMBus interface. Output Disable Logic Output for phases 2-4. This pin is actively pulled low when the EN input is low or when VCC is below its UVLO threshold to signal to the Driver IC that the driver high-side and low-side outputs should go low. Output Disable Logic Output for phase one. This pin is actively pulled low when the EN input is low or when VCC is below its UVLO threshold to signal to the Driver IC that the driver high-side and low-side outputs should go low. Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be left open. Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the ADP3120A. Connecting the PWM4, and PWM3 outputs to VCC causes that phase to turn off, allowing the NCP4200 to operate as a 2-phase controller. Supply Voltage for the Device. Voltage Identification DAC Inputs. These eight pins are pulled down to GND, providing a logic zero if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.375 V to 1.6 V. Power Save Interface. System signal to select single phase option. Power-Good Output. Open-drain output that signals when the output voltage is outside of the proper operating range.
17 18 19
CSSUM CSCOMP ILIMITFS
20
ODN
21
OD1
22 to 25 26 to 29
SW4 to SW1 PWM4 to PWM1
30 31 to 38
VCC VID7 to VID0
39 40
PSI PWRGD
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NCP4200
ELECTRICAL CHARACTERISTICS VIN = 5.0 V, FBRTN = GND for typical values TA = 0C to 85C, unless otherwise noted.
(Note 1 and 3). Parameter REFERENCE CURRENT Reference Bias Voltage Reference Bias Current ERROR AMPLIFIER Output Voltage Range (Note 1) Accuracy VCOMP VFB VFB(BOOT) Load Line Positioning Accuracy Load Line Range Load Line Attenuation Differential Non-linearity Input Bias Current Offset Accuracy FBRTN Current Output Current Gain Bandwidth Product Slew Rate BOOT Voltage Hold Time VID INPUTS Input Low Voltage Input High Voltage Input Current VID Transition Delay Time (Note 1) No CPU Detection Turn-Off Delay Time OSCILLATOR Frequency Range (Note 1) Frequency Variation fOSC fPHASE TA = 25C, RT = 460kW, 4-phase TA = 25C, RT = 220kW, 4-phase TA = 25C, RT = 120kW, 4-phase RT = 500 kW to GND RAMPADJ - FB, VFB = 1.0 V, IRAMPADJ = -50 mA 0.25 220 260 500 850 2.03 6.0 290 MHz kHz VIL(VID) VIH(VID) IIN(VID) VID code change to FB change VID code change to PWM going low 200 5 VID(X) VID(X) 0.8 -5.0 0.3 V V mA ns ms tBOOT IFBRTN ICOMP GBW(ERR) FB forced to VOUT - 3% COMP = FB COMP = FB Internal Timer IFB IFB = IIREF VR Offset Register = 111111, VID = 1.0 V VR Offset Register = 011111, VID = 1.0 V Relative to nominal DAC output, referenced to FBRTN (Note 2) In startup 0 -7.7 1.091 -77 -350 0 -1.0 14.2 16 -193.75 193.75 70 500 20 25 2.0 200 1.1 -80 4.4 +7.7 1.109 -83 0 100 +1.0 17.7 V mV V mV mV % LSB mA mV mA mA MHz V/ms ms VIREF IIREF RIREF = 121 kW 1.75 1.8 16 1.9 V mA Symbol Conditions Min Typ Max Unit
Output Voltage RAMPADJ Output Voltage RAMPADJ Input Current Range CURRENT SENSE AMPLIFIER Offset Voltage Input Bias Current, CSREF Input Bias Current, CSSUM Gain Bandwidth Product Slew Rate Input Common-Mode Range Output Voltage Range Output Current Current Limit Latchoff Delay Time
VRT VRAMPADJ IRAMPADJ VOS(CSA) IBIAS(CSREF) IBIAS(CSSUM) GBW(CSA)
1.93 -50 5.0
2.13 +50 60 +0.7 +20 +10
V mV mA mV mA nA MHz V/ms
CSSUM - CSREF (Note 3) CSREF = 1.0 V CSREF = 1.0 V CSSUM = CSCOMP CCSCOMP = 10 pF CSSUM and CSREF
-0.7 -20 -10 10 10 0 0.05 500
3.0 3.0 8.0
V V mA ms
ICSCOMP Internal Timer
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NCP4200
ELECTRICAL CHARACTERISTICS VIN = 5.0 V, FBRTN = GND for typical values TA = 0C to 85C, unless otherwise noted.
(Note 1 and 3). Parameter PSI Input Low Voltage Input High Voltage Input Current Assertion Timing De-assertion Timing TRDET Output Low Voltage IMON Clamp Voltage Accuracy Output Current Offset CURRENT LIMIT COMPARATOR ILIM Bias Current ILIM CSREF - CSCOMP)/RILIM, (CSREF - CSCOMP) = 150 mV, RILIMC = 7.5 kW 4/3 x IIREF -600 SW(X) = 0 V SW(X) = 0 V SW(X) = 0 V Phase Bal Registers = 00000 Phase Bal Registers = 11111 14 8 -6.0 -25 +25 18 12 20 mA -3.0 10 x (CSREF - CSCOMP)/RILIM 1.0 -3.0 1.15 3.0 800 3.0 V % mA mV VOL IOUT = -6 mA 150 300 mV Fsw = 300 kHz Fsw = 300 kHz 0.8 -5.0 3.3 825 0.3 V V mA ms ns Symbol Conditions Min Typ Max Unit
Current Limit Threshold Current CURRENT BALANCE AMPLIFIER Common-Mode Range Input Resistance Input Current Input Current Matching Phase Balance Adjustment Range Low Phase Balance Adjustment Range High DELAY TIMER Internal Timer Timer Range Low Timer Range High SOFT-START Internal Timer Timer Range Low Timer Range High ENABLE INPUT Input Low Voltage Input High Voltage Input Current Delay Time ODN / OD1 OUTPUTS Output Low Voltage Output High Voltage ODN/OD1 Pulldown Resistor
ICL VSW(X)CM RSW(X) ISW(X) ISW(X)
20 +200 21 28 +6.0
mA mV kW mA % % %
Delay Time Register = 011 Delay Time Register = 000 Delay Time Register = 111 Soft-Start Slope Register = 010 Soft-Start Slope Register = 000 Soft-Start Slope Register = 111 VIL(EN) VIH(EN) IIN(EN) tDELAY(EN) VOL(OD1) VOH(ODN/1) EN > 0.8V , Internal Delay IOD(SINK) = -400 mA IOD(SOURCE) = 400 mA 4.0 0.8
2.0 0.5 4.0 0.5 0.1 1.5 0.3 -1.0 2.0 160 5.0 60 500
ms ms ms V/ms V/ms V/ms V V mA ms mV V kW
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NCP4200
ELECTRICAL CHARACTERISTICS VIN = 5.0 V, FBRTN = GND for typical values TA = 0C to 85C, unless otherwise noted.
(Note 1 and 3). Parameter POWER-GOOD COMPARATOR Undervoltage Threshold Undervoltage Adjustment Range Low Undervoltage Adjustment Range High Overvoltage Threshold Overvoltage Adjustment Range Low Overvoltage Adjustment Range High Output Low Voltage Power Good Delay Time During Soft-Start VID Code Changing VID Code Static Crowbar Trip Point Crowbar Adjustment Range Crowbar Reset Point Crowbar Delay Time VID Code Changing VID Code Static PWM OUTPUTS Output Low Voltage Output High Voltage PMBus INTERFACE Logic High Input Voltage Logic Input Low Voltage Hysteresis SDA Output Low Voltage Input Current Input Capacitance Clock Frequency SCL Falling Edge to SDA Valid Time ALERT / FAULT OUTPUTS Output Low Voltage Output High Leakage Current ANALOG / DIGITAL CONVERTER ADC Input Voltage Range Total Unadjusted Error (TUE) Differential Non-linearity (DNL) Conversion Time, Voltage Channel 8 Bits Averaging Enabled (32 averages) 0 1 1.0 80 2 V % LSB ms VOL IOH IOUT = -6 mA VOH = 5.0 V 0.4 1.0 V uA VOL IIH; IIL CSCL, SDA fSCL ISDA = -6mA -1.0 5.0 400 1.0 VIH(SDA, SCL) VIL(SDA, SCL) 500 0.4 1.0 2.1 0.8 V V mV V mA pF kHz ms IPWM(SINK) = -400 mA IPWM(SOURCE) = 400 mA VOL(PWM) VOH(PWM) 4.0 160 5.0 500 mV V tCROWBAR VCROWBAR Relative to DAC output, PWRGD_Hi = 00 PWRGD_HI Register Relative to FBRTN Overvoltage to PWM going low 100 250 400 ms ns 200 150 250 300 Internal Timer 100 2.0 250 200 300 400 300 350 ms ms ns mV mV mV VOL(PWRGD) VPWRGD(OV) VPWRGD(UV) Relative to nominal DAC output PWRGD_LO Register = 000 PWRGD_LO Register = 111 Relative to DAC output, PWRGD_Hi = 00 PWRGD_Hi Register = 11 PWRGD_Hi Register = 00 IPWRGD(SINK) = -4 mA 200 -600 -500 -500 -150 300 150 300 150 300 400 -400 mV mV mV mV mV mV mV Symbol Conditions Min Typ Max Unit
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NCP4200
ELECTRICAL CHARACTERISTICS VIN = 5.0 V, FBRTN = GND for typical values TA = 0C to 85C, unless otherwise noted.
(Note 1 and 3). Parameter SUPPLY VCC (Note 1) DC Supply Current UVLO Turn-On Current UVLO Threshold Voltage UVLO Turn-Off Voltage VCC3 Output Voltage VCC3 VUVLO VCC rising VCC falling IVCC3 = 1 mA 3.0 10 4.1 3.3 3.6 IVCC VCC VSYSTEM = 13.2 V, RSHUNT = 340 W 4.70 5.25 20 6.5 5.75 25 11 V mA mA V V V Symbol Conditions Min Typ Max Unit
1. Refer to Electrical Characteristics and Application Information for Safe Operating Area. 2. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TJ = TA = 25C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 3. Values based on design and/or characterization.
TYPICAL CHARACTERISTICS
2500
2000
Frequency (kHz)
1500 PWM1 1000
500
0
0
100
200
300
400 RT (kW)
500
600
700
800
900
Figure 3. Master Clock Frequency vs. RT
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NCP4200
TEST CIRCUITS
8 BIT VID CODE
680 W PWRGD PSI VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 +1m F VCC PWM1 PWM2 PWM3 PWM4 SW1 SW2 SW3 SW4 OD1 100 nF
+12 V 680 W
VCC3 ALERT FAULT SDA +1.25 V SDL EN GND IMON IREF RT
NCP4200
RAMPADJ TRDET FBRTN COMP FB CSREF
121 kW
20 k W 1kW 100 nF
Figure 4. Closed-Loop Output Voltage Accuracy
CSCOMP ILIMITFS ODN
CSSUM
10 k W
12 V 12 V
ADP4200
680 W VCC
30
ADP4200
680 W
30
680 W
680 W
VCC 10 k W
COMP
14
CSCOMP
18
FB
15
39 k W
100 nF CSSUM
17
- CSREF
19
1 kW
16
CSREF 1V
+
VID DAC
1V
7
GND
VOS =
CSCOMP - 1 V 40
GND
7
DV FB = FB DV = 80mV - FB DV = 0 mV
Figure 5. Current Sense Amplifier VOS
Figure 6. Positioning Voltage
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NCP4200
Description
The NCP4200 is a 4 Phase DC-DC regulator with a PMBus Interface. A typical application circuit is shown in Figure 2.
Startup Sequence
The NCP4200 follows the startup sequence shown in Figure 7. After both the EN and UVLO conditions are met, a programmable internal timer goes through one delay cycle TD1. This delay cycle is programmed using Delay Command, default delay = 2 ms, see Table 2 for programmable values. The first six clock cycles of TD2 are blanked from the PWM outputs and used for phase detection as explained in the following section. Then the programmable internal soft-start ramp is enabled (TD2) and the output comes up to the boot voltage of 1.1 V. The boot hold time is also set by Delay Command. This second delay cycle is called TD3. During TD3 the processor VID pins settle to the required VID code. When TD3 is over, the NCP4200 reads the VID inputs and soft-starts either up or down to the final VID voltage (TD4). After TD4 has been completed and the PWRGD masking time (equal to VID OTF masking) is finished, a third cycle of the internal timer sets the PWRGD blanking (TD5). The internal delay and soft-start times are programmable using the serial interface, the Delay Command and the Soft-Start Commands.
UVLO THRESHOLD
section. The current limit timer is set to 4 times the delay timer. The delay timer is programmed using Bits <2:0> of the Ton Delay command (0xD4). The delay can be programmed between 0.5 msec and 4 msec. Table 1 provides the programmable delay times.
Table 1. Delay Codes
Code 000 001 010 011 100 101 110 111 Delay (msec) 0.5 1 1.5 2 = default 2.5 3 3.5 4
Soft-Start
5.0 V SUPPLY VTT I/O (NCP4200 EN) VCC_CORE
0.85 V
TD1
TD3 VBOOT (1.1 V)
V VID TD4
VR READY (NCP4200 PWRGD)
TD2
The Soft-Start slope for the output voltage is set by an internal timer. The default value is 0.5 V/msec, which can be programmed through the PMBus interface. After TD1 and the phase detection cycle have been completed, the SS time (TD2 in Figure 2) starts. The SS circuit uses the internal VID DAC to increase the output voltage in 6.25 mV steps up to the 1.1 V boot voltage. Once the SS circuit has reached the boot voltage, the boot voltage delay time (TD3) is started. The end of the boot voltage delay time signals the beginning of the second soft-start time (TD4). The SS voltage changes from the boot voltage to the programmed VID DAC voltage (either higher or lower) using 6.25 mV steps. The soft-start slew rate is programmed using Bits <2:0> of the Ton_Rise (0xD5) command code. Table 2 provides the soft-start values.
Table 2. Slew Rate Codes
Code 000 001 010 011 100 101 110 111 Slew Rate (V/msec) 0.1 0.3 0.5 = default 0.7 0.9 1.1 1.3 1.5
50 ms CPU VID INPUTS VID INVALID
TD5 VID VALID
Figure 7. Startup Sequence Internal Delay Timer
An internal timer sets the delay times for the start up sequence, TD1, TD3 and TD5. The default time is 2 msec, which can be changed using the PMBus interface. This timer is used for multiple delay timings (TD1, TD3 and TD5) during the startup sequence. Also, it is used for timing the current limit latchoff as explained in the Current Limit
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NCP4200
Figure 8 shows typical startup waveforms for the NCP4200. phases in use. If all phases are in use, divide by 4. If 2 phases are in use then divide by 2.
Output Voltage Differential Sensing
The NCP4200 combines differential sensing with a high accuracy VID DAC and reference, and a low offset error amplifier. This maintains a worst-case specification of 9 mV differential sensing error over its full operating output voltage and temperature range. The output voltage is sensed between the FB pin and FBRTN pin. FB is connected through a resistor, RB, to the regulation point, usually the remote sense pin of the microprocessor. FBRTN is connected directly to the remote sense ground point. The internal VID DAC and precision reference are referenced to FBRTN, which has a minimal current of 70 mA to allow accurate remote sensing. The internal error amplifier compares the output of the DAC to the FB pin to regulate the output voltage.
Figure 8. Typical Startup Waveforms Phase Detection Output Current Sensing
During startup, the number of operational phases and their phase relationship is determined by the internal circuitry that monitors the PWM outputs. Normally, the NCP4200 operates as a 4-phase PWM controller. To operate as a 3-Phase Controller: connect PWM4 to VCC. To operate as a 2-Phase Controller: connect PWM3 and PWM4 to VCC. To operate as a single phase controller: connect PMW2, PWM3, and PWM4 to VCC. Prior to soft-start, while EN is high the PWM4, PWM3 and PWM2 pins sink approximately 100 mA each. An internal comparator checks each pin's voltage vs. a threshold of 3.0 V. If the pin is tied to VCC, it is above the threshold. Otherwise, an internal current sink pulls the pin to GND, which is below the threshold. PWM1 is low during the phase detection interval that occurs during the first six clock cycles of TD2. After this time, if the remaining PWM outputs are not pulled to VCC, the 100 mA current sink is removed, and they function as normal PWM outputs. If they are pulled to VCC, the 100 mA current source is removed, and the outputs are put into a high impedance state. The PWM outputs are logic-level devices intended for driving fast response external gate drivers such as the ADP3121. Because each phase is monitored independently, operation approaching 100% duty cycle is possible. In addition, more than one output can be on at the same time to allow overlapping phases.
Master Clock Frequency
The clock frequency of the NCP4200 is set with an external resistor connected from the RT pin to ground. The frequency follows the graph in Figure 3. To determine the frequency per phase, the clock is divided by the number of
The NCP4200 provides a dedicated Current Sense Amplifier (CSA) to monitor the total output current for proper voltage positioning vs. load current, for the IMON output and for current limit detection. Sensing the load current at the output gives the total real time current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element such as the low-side MOSFET. This amplifier can be configured in several ways, depending on the objectives of the system, as follows: * Output inductor DCR sensing without a thermistor for lower cost. * Output inductor DCR sensing with a thermistor for improved accuracy with inductor temperature tracking. * Sense resistors for highest accuracy measurements. The positive input of the CSA is connected to the CSREF pin, which is connected to the average output voltage. The inputs to the amplifier are summed together through resistors from the sensing element, such as the switch node side of the output inductors, to the inverting input CSSUM. The feedback resistor between CSCOMP and CSSUM sets the gain of the amplifier and a filter capacitor is placed in parallel with this resistor. The gain of the amplifier is programmable by adjusting the feedback resistor. This difference signal is used internally to offset the VID DAC for voltage positioning. This difference signal can be adjusted between 50% and 150% of the external value using the PMBus Load-line Calibration (0xDE) and Load-line Set (0xDF) commands. The difference between CSREF and CSCOMP is used as a differential input for the current limit comparator. To provide the best accuracy for sensing current, the CSA is designed to have a low offset input voltage. Also, the sensing gain is determined by external resistors to make it extremely accurate.
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NCP4200
The CPU current can also be monitored over the PMBus. The current limit and the load-line can be adjusted from the circuit component values over the PMBus.
Current Limit Set-Point
The current limit threshold on the NCP4200 is programmed by a resistor between the ILIMFS pin and the CSCOMP pin. The ILIMFS current, IILIMFS, is compared with an internal current reference of 20 mA. If IILIMFS exceeds 20 mA then the output current has exceeded the limit and the current limit protection is tripped.
I ILIMFS + V ILIMFS * V CSCOMP R ILIMFS V CSREF * V CSCOMP R ILIMFS RL I LOAD
(eq. 1)
Where VILIMFS = VCSREF
I ILIMFS +
(eq. 2)
R V CSREF * V CSCOMP + CS R PH
longer than the delay time during the startup sequence. The current limit delay time only starts after TD5 has completed. If there is a current limit during startup, the NCP4200 will go through TD1 to TD5 and then start the latchoff time. Because the controller continues to cycle the phases during the latchoff delay time, if the short is removed before the timer is complete, the controller can return to normal operation. The latchoff function can be reset by either removing/ reapplying the supply voltage to the NCP4200, or by toggling the EN pin low for a short time. During startup when the output voltage is below 200 mV, a secondary current limit is active. This is necessary because the voltage swing of CSCOMP cannot go below ground. This secondary current limit limits the internal COMP voltage to the PWM comparators to 1.5 V. This limits the voltage drop across the low-side MOSFETs through the current balance circuitry. Typical overcurrent latchoff waveforms are shown in Figure 9.
Assuming that:
R CS R PH R L + 1 mW
(eq. 3)
i.e. the external circuit is set up for a 1 mW load-line then the RILIMFS is calculated as follows:
I ILIMFS + 1 mW I LOAD R ILIMITFS
(eq. 4)
Assuming we want a current limit of 150 A that means that ILIMFS must equal 20 mA at that load.
20 mA + 1 mW 150 A + 7.5 kW R ILIMITFS
(eq. 5)
Solving this equation for RLIMITFS we get 7.5 kW. The current limit threshold can be modified from the resistor programmed value by using the PMBus interface using Bits <4:0> of the Current Limit Threshold command (0xE2). The limit is programmable between 50% of the external limit and 146.7% of the external limit. The resolution is 3.3%. Table 3 gives some examples codes.
Table 3. Current Limit
Code 0 0000 0 0001 1 0000 1 0001 1 1110 1 1111 Current Limit (% of External Limit) 50% 53.3% 100% = default 103.3% 143.3% 146.7%
Figure 9. Overcurrent Latchoff Waveforms
An inherent per phase current limit protects individual phases if one or more phases stop functioning because of a faulty component. This limit is based on the maximum normal mode COMP voltage.
Output Current Monitor
IMON is an analog output from the NCP4200 representing the total current being delivered to the load. It outputs an accurate current that is directly proportional to the current set by the ILIMFS resistor.
I IMON + 10 I ILIMFS
(eq. 6)
Current Limit, Short-Circuit and Latchoff Protection
If the current limit is reached and TD5 has completed, an internal latchoff delay time will start, and the controller will shut down if the fault is not removed. This delay is four times
The current is then run through a parallel RC connected from the IMON pin to the FBRTN pin to generate an accurately scaled and filtered voltage as per the specification. The size of the resistor is used to set the IMON scaling. The scaling is set such that IMON = 900 mV at the TDC current of the processor. This means that the RIMON resistor should be chosen as follows.
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From the Current Limit Set-point paragraph we know the following:
1 mW I LOAD I ILIMFS + R LIMIFS
(eq. 7)
Current Control Mode and Thermal Balance
I IMON + 10
1 mW I LOAD R LIMFS
For a 150 A current limit RLIMFS = 7.5 kW. Assuming the TDC = 135 A then VMON should equal 900 mV when ILOAD = 135 A. When ILOAD = 135 A, IMON equals:
I IMON + 10 1 mW 135 A + 180 mA 7.5 kW R MON
(eq. 8)
V IMON + 900 mV + 180 mA
This gives a value of 5 kW for RMON. If the TDC and OCP limit for the processor have to be changed the because the ILIMITFS resistor sets up both the current limit and also the current out of the IMON pin, as explained earlier. The IMON pin also includes an active clamp to limit the IMON voltage to 1.15 V MAX while maintaining accuracy at 900 mV full scale.
Active Impedance Control Mode
The NCP4200 has individual inputs (SW1 to SW4) for each phase that are used for monitoring the per phase current. This information is combined with an internal ramp to create a current balancing feedback system that has been optimized for initial current balance accuracy and dynamic thermal balancing during operation. This current balance information is independent of the average output current information used for positioning. The magnitude of the internal ramp can be set to optimize the transient response of the system. It also monitors the supply voltage for feed-forward control for changes in the supply. A resistor connected from the power input voltage to the RAMPADJ pin determines the slope of the internal PWM ramp. The balance between the phases can be programmed using the PMBus Phase Bal SW(x) commands (0xE3 to 0xE6). This allows each phase to be adjusted if there is a difference in temperature due to layout and airflow considerations. The phase balance can be adjusted from a default gain of 5 (Bits 4:0 = 10000). The minimum gain programmable is 3.75 (Bits 4:0 = 00000) and the max gain is 6.25 (Bits 4:0 = 11111).
Voltage Control Mode
For controlling the dynamic output voltage droop as a function of output current, the CSA gain and load-line programming can be scaled to be equal to the droop impedance of the regulator times the output current. This droop voltage is then used to set the input control voltage to the system. The droop voltage is subtracted from the DAC reference input voltage directly to tell the error amplifier where the output voltage should be. This allows enhanced feed forward response.
Load Line Setting
The load-line is programmable over the PMBus on the NCP4200. It is programmed using the Load-line Calibration (0xDE) and Load-line Set (0xDF) commands. The load-line can be adjusted between 0% and 100% of the external RCSA. In this example RCSA = 1 mW RO needs to 0.8 mW therefore programming the Load-line Calibration + Load-line Set register to give a combined percentage of 80% will set the RO to 0.8 mW
Table 4. Load-line Commands
Code 0 0000 0 0001 1 0000 1 0001 1 1110 1 1111 Load-line (as a percentage of RCSA) 0% 3.226% 51.6% = default 53.3% 96.7% 100%
A high gain, high bandwidth, voltage mode error amplifier is used for the voltage mode control loop. The control input voltage to the positive input is set via the VID logic according to the voltages listed in Table 10. The VID code is set using the VID Input pins or it can be programmed over the PMBus using the VOUT_Command. By default, the NCP4200 outputs a voltage corresponding to the VID Inputs. To output a voltage following the VOUT_Command the user first needs to program the required VID Code. Then the VID_EN Bits need to be enabled. The following is the sequence: 1. Program the required VID Code to the VOUT_Command code (0x21). 2. Set the VID_EN bit (Bit 3) in the VR Config 1 A (0xD2) and on the VR Config 1B (0xD3). This voltage is also offset by the droop voltage for active positioning of the output voltage as a function of current, commonly known as active voltage positioning. The output of the amplifier is the COMP pin, which sets the termination voltage for the internal PWM ramps. The negative input (FB) is tied to the output sense location with Resistor RB and is used for sensing and controlling the output voltage at this point. A current source (equal to IREF) from the FB pin flowing through RB is used for setting the no load offset voltage from the VID voltage. The no load voltage is negative with respect to the VID DAC for Intel CPU's.
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The value of RB can be found using the following equation:
RB + V VID * V ONL I FB
(eq. 9)
Table 6. Transition Rate Codes
Code 000 001 010 011 100 101 110 111 Transition Rate (V/msec) 1 3 5 = default 7 9 11 13 15
An offset voltage can be added to the control voltage over the serial interface. This is done using Bits <5:0> of the VOUT_TRIM (0xDB) and VOUT_CAL (0xDC) Commands. The max offset that can be applied is 193.75 mV (even if the sum of the offsets > 193.75 mV). The LSB size is 6.25 mV. A positive offset is applied when Bit 5 = 0. A negative offset is applied when Bit 5 = 1.
Table 5. Offset Codes
VOUT_ TRIM CODE 00 1000 10 0001 00 1111 TRIM OFFSET VOLTAGE 50 mV -6.25 mV 93.75 mV VOUT_ CAL CODE 00 0010 10 1110 10 0001 CAL OFFSET VOLTAGE 12.5 mV -87.5 mV -6.25 mV TOTAL OFFSET VOLTAGE 62.5 mV -93.75 mV 87.5 mV
Enhanced Transients Mode
Dynamic VID
The NCP4200 has the ability to respond to dynamically changing VID inputs while the controller is running. This allows the output voltage to change while the supply is running and supplying current to the load. This is commonly referred to as Dynamic VID (DVID). A DVID can occur under either light or heavy load conditions. The processor signals the controller by changing the VID inputs (or by programming a new VOUT_Command) in a single or multiple steps from the start code to the finish code. This change can be positive or negative. When a VID bit changes state, the NCP4200 detects the change and ignores the DAC inputs for a minimum of 200 ns. This time prevents a false code due to logic skew while the VID inputs are changing. Additionally, the first VID change initiates the PWRGD and CROWBAR blanking functions for a minimum of 100 ms to prevent a false PWRGD or CROWBAR event. Each VID change resets the internal timer. If a VID off code is detected the NCP4200 will wait for 5 msec to ensure that the code is correct before initiating a shutdown of the controller. The NCP4200 also uses the TON_Transition command code (0xD6) to limit the DVID slew rates. These can be encountered when the system does a large single VID step for power state changes, thus the DVID slew rate needs to be limited to prevent large inrush currents. The transition slew rate is programmed using Bits <2:0> of the Ton_Transition (0xD6) command code. Table 6 provides the soft-start values.
The NCP4200 incorporates enhanced transient response for both load step up and load release. For load step up it senses the output of the error amp to determine if a load step up has occurred and then sequences on the appropriate number of phases to ramp up the output current. For load release, it also senses the output of the error amp and uses the load release information to trigger the TRDET pin, which is then used to adjust the error amp feedback for optimal positioning. This is especially important during high frequency load steps. Additional information is used during load transients to ensure proper sequencing and balancing of phases during high frequency load steps as well as minimizing the stress on components such as the input filter and MOSFETs.
Reference Current
The IREF pin is used to set an internal current reference. This reference current sets IFB. A resistor to ground programs the current based on the 1.8 V output.
I REF + 1.8 V R IREF
(eq. 10)
Typically, RIREF is set to 121 kW to program IREF = 15 mA.
I FB + I REF + 15 mA Power Good Monitoring
(eq. 11)
The power good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open-drain output whose high level (when connected to a pullup resistor) indicates that the output voltage is within the nominal limits. The nominal limits specified in the specifications above based on the VID voltage setting. PWRGD goes low if the output voltage is outside of this specified range, if the VID DAC inputs are in no CPU mode, or whenever the EN pin is pulled low. PWRGD is blanked during a DVID event for a period of 100 ms to prevent false signals during the time the output is changing.
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The PWRGD circuitry also incorporates an initial turn-on delay time (TD5). Prior to the SS voltage reaching the programmed VID DAC voltage and the PWRGD masking time finishing, the PWRGD pin is held low. Once the SS circuit reaches the programmed DAC voltage, the internal timer operates. The default range for the PWRGD comparator is +300 mV and -500 mV. However these values can be adjusted over the PMBus. The high limit is programmed using Bits <1:0> of Command Code 0xE0 and the low limit is programmed using Bits <2:0> of Command code 0xE1. The following is a table of the programmable values.
Table 7. PWRGD High Limits
Code 00 01 10 11 PWRGD High Limits +300mV (default) +250 mV +200 mV +150 mV
The actual phases enabled, depends upon how many phases are enabled for normal operation. For example if 4 phases are enabled normally and 2 during PSI, then Phase 1 and Phase 3 will be enabled during PSI.
Output Crowbar
As part of the protection for the load and output components of the supply, the PWM outputs are driven low (turning on the low-side MOSFETs) when the output voltage exceeds the upper crowbar threshold. This crowbar action stops once the output voltage falls below the release threshold of approximately 300 mV. The value for the crowbar limit follows the programmable PWRGD high limit. Turning on the low-side MOSFETs pulls down the output as the reverse current builds up in the inductors. If the output overvoltage is due to a short in the high-side MOSFET, this action current limits the input supply, or blows its fuse protecting the microprocessor from being destroyed.
Output Enable and UVLO
Table 8. PWRGD Low Limits
Code 000 001 010 011 100 101 110 111 PWRGD Low Limits -500mV (default) -450 mV -400 mV -350 mV -300 mV -250 mV -200 mV -150 mV
Power State Indicator
The PSI pin is an input used to determine the operating state of the load. If this input is pulled low, the load is in a low power state and the controller asserts the ODN pin low, which can be used to disable phases and maintain better efficiency at lighter loads. The sequencing into and out of low power operation is maintained to minimize output deviations as well as providing full power load transients immediately after exiting a low power state. The user can program how many phases are enabled when PSI is asserted. By default only phase 1 is enabled. The number of phases enabled can be changed over the PMBus. However extreme care should be taken to ensure that OD1 is connected to all phases enabled during PSI. The number of phases enabled during PSI is programmed using Bits 6 and 7 of the MFR Config Command (0xD1).
Table 9. # Phases Enabled During PSI
Code 00 01 10 11 PWRGD High Limits 1-Phase (default) 2-Phases 1-Phase 1-Phase
For the NCP4200 to begin switching the input, supply current to the controller must be higher than the UVLO threshold and the EN pin must be higher than its 0.8 V threshold. This initiates a system startup sequence. If either UVLO or EN is less than their respective thresholds, the NCP4200 is disabled. This holds the PWM outputs at ground and forces PWRGD, ODN and OD1 signals low. In the application circuit (see Figure 2), the OD1 pin should be connected to the OD inputs of the external drivers for the phases that are always on. The ODN pin should be connected to the OD inputs of the external drivers on the phases that are shut down during low power operation. Grounding the driver OD inputs disables the drivers such that both DRVH and DRVL are grounded. This feature is important in preventing the discharge of the output capacitors when the controller is shut off. If the driver outputs are not disabled, a negative voltage can be generated during output due to the high current discharge of the output capacitors through the inductors.
Voltage Monitoring
The NCP4200 can monitor the voltage on the EN pin and reports this back in a register. The ADC range for the voltage measurements is 0 V to 2.0 V. Voltages greater than 2.0 V can be monitored using a resistor divider network. Voltage measurements are 10 bits wide.
Shunt Resistor
The NCP4200 uses a shunt to generate 5.0 V from the 12 V supply range. A trade-off can be made between the power dissipated in the shunt resistor and the UVLO threshold. Figure 10 shows the typical resistor value needed to realize certain UVLO voltages. It also gives the maximum power dissipated in the shunt resistor for these UVLO voltages.
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400 0.325 0.3 0.275 300 0.25 250 0.225 200 0.2 0.175 8 9 10 11 12 13 14 15 16 Rshunt Pshunt 2-0603 Limit 2-0805 Limit
350
150
ICC (UVLO)
Figure 10. Typical Shunt Resistor Value and Power Dissipation for Different UVLO Voltage
The maximum power dissipated is calculated using Equation:
P MAX + V IN(MAX) * V CC(MIN) R SHUNT
2
(eq. 12)
where: VIN(MAX) is the maximum voltage from the 12 V input supply (if the 12 V input supply is 12 V 5%, VIN(MAX) = 12.6 V; if the 12 V input supply is 12 V 10%, VIN(MAX) = 13.2 V). VCC(MIN) is the minimum VCC voltage of the NCP4200. This is specified as 4.75 V. RSHUNT is the shunt resistor value. The CECC standard specification for power rating in surface-mount resistors is: 0603 = 0.1 W, 0805 = 0.125 W, 1206 = 0.25 W.
PMBus Interface
Control of the NCP4200 is carried out using the PMBus Interface. The physical protocol for PMBus closely matches that of SMBus. The NCP4200 is connected to this bus as a slave device, under the control of a master controller. Data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high might be interpreted as a stop signal. The number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the tenth clock pulse to assert a stop
condition. In read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse; this is known as No Acknowledge. The master takes the data line low during the low period before the tenth clock pulse, and then high during the tenth clock pulse to assert a stop condition. Any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. In the NCP4200, write operations contain one, two or three bytes, and read operations contain one or two bytes. The command code or register address determines the number of bytes to be read or written, See the Register Map for more information. To write data to one of the device data registers or read data from it, the address pointer register must be set so that the correct data register is addressed (i.e. command code), and then data can be written to that register or read from it. The first byte of a read or write operation always contains an address that is stored in the address pointer register. If data is to be written to the device, the write operation contains a second data byte that is written to the register selected by the address pointer register. This write byte operation is shown in Figure 12. The device address is sent over the bus, and then R/W is set to 0. This is followed by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. The second data byte is the data to be written to the internal data register. 1. The read byte operation is shown in Figure 13. First the command code needs to be written to the NCP4200 so that the required data is sent back. This is done by performing a write to the NCP4200 as before, but only the data byte containing the register address is sent, because no data is written to the register. A repeated start is then issued and a read operation is then performed consisting of the serial bus address; R/W bit set to 1, followed by the data byte read from the data register. 2. It is not possible to read or write a data byte from a data register without first writing to the address pointer register, even if the address pointer register is already at the correct value. 3. In addition to supporting the send byte, the NCP4200 also supports the read byte, write byte, read word and write word protocols. (See System Management Bus Specifications Rev. 2.0 and the PMBus Specification Rev 1.1 Part I and Part II for more information.)
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1 SCL 9 1 9
SDA 1 START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE 1 0 0 0 A1 A0 R/W ACK. BY NCP4200 FRAME 2 COMMAND CODE D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY STOP BY NCP4200 MASTER
Figure 11. Send Byte
1 SCL 9 1 9
SDA 1 START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE 1 SCL (CONTINUED) 1 0 0 0 A1 A0 R/W ACK. BY NCP4200 FRAME 2 COMMAND CODE 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY NCP4200
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY NCP4200 STOP BY MASTER
FRAME 3 DATA BYTE
Figure 12. Write Byte
1 SCL 9 1 9
SDA 1 START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE 1 SCL 9 1 1 0 0 0 A1 A0 R/W ACK. BY NCP4200 D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY NCP4200
FRAME 2 COMMAND CODE 9
SDA 1 REPEATED START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE 1 0 0 0 A1 A0 R/W ACK. BY NCP4200 D7
D6
D5
D4
D3
D2
D1
D0 NO ACK. BY STOP BY MASTER MASTER
FRAME 2 DATA BYTE FROM NCP4200
Figure 13. Read Byte Write Operations Send Byte
The PMBus specification defines several protocols for different types of read and writes operations. The ones used in the NCP4200 are discussed in this section. The following abbreviations are used in the diagrams: S--START P--STOP R--READ W--WRITE A--ACKNOWLEDGE A--NO ACKNOWLEDGE The NCP4200 uses the following PMBus write protocols.
In this operation, the master device sends a single command byte to a slave device as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserts ACK on SDA. 6. The master asserts a stop condition on SDA and the transaction ends.
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For the NCP4200, the send byte protocol is used to clear faults. This operation is shown in Figure 14.
1 2 3 4 COMMAND CODE 56 AP SLAVE S WA ADDRESS
Block Write
Figure 14. Send Byte Command
If the master is required to read data from the register immediately after setting up the address, it can assert a repeat start condition immediately after the final ACK and carry out a single byte read without asserting an intermediate stop condition.
Write Byte
In this operation, the master device sends a command byte and one data byte to the slave device as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserts ACK on SDA. 6. The master sends a data byte. 7. The slave asserts ACK on SDA. 8. The master asserts a stop condition on SDA and the transaction ends. The byte write operation is shown in Figure 15.
1 2 3 4 COMMAND CODE 5 6 7 8 SLAVE S WA ADDRESS A DATA A P
In this operation, the master device sends a command byte and a byte count followed by the stated number of data bytes to the slave device as follows: 1. The master device asserts a START condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code 5. The slave asserts ACK on SDA 6. The master sends the byte count N 7. The slave asserts ACK on SDA 8. The master sends the first data byte 9. The slave asserts ACK on SDA 10. The master sends the second data byte. 11. The slave asserts ACK on SDA 12. The master sends the remainder of the data byes 13. The slave asserts an ACK on SDA after each data byte. 14. After the last data byte the master asserts a STOP condition on SDA
1 2 3 4 COMMAND CODE 11 A 5 A 6 7 8 9 SLAVE S WA ADDRESS 10 DATA BYTE 2 BYTE COUNT A =N 12 DATA BYTE N 13 A 14 P DATA A BYTE 1
... ...
Figure 17. Block Write to a Register Read Operations
Figure 15. Single Byte Write to a Register Write Word
The NCP4200 uses the following PMBus read protocols.
Read Byte
In this operation, the master device sends a command byte and two data bytes to the slave device as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserts ACK on SDA. 6. The master sends the first data byte. 7. The slave asserts ACK on SDA. 8. The master sends the second data byte. 9. The slave asserts ACK on SDA. 10. The master asserts a stop condition on SDA and the transaction ends. The word write operation is shown in Figure 16.
1 2 3 4 COMMAND CODE 5 6 7 8 9 10 SLAVE S WA ADDRESS DATA DATA A A AP (LSB) (MSB)
In this operation, the master device receives a single byte from a slave device as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserted ACK on SDA. 6. The master sends a repeated start condition on SDA. 7. The master sends the 7 bit slave address followed by the read bit (high). 8. The slave asserts ACK on SDA. 9. The slave sends the Data Byte. 10. The master asserts NO ACK on SDA. 11. The master asserts a stop condition on SDA and the transaction ends.
1 S 2 3 4 COMMAND CODE 5 6 7 8 9 10 11 P SLAVE WA ADDRESS AS SLAVE R A DATA A ADDRESS
Figure 16. Single Word Write to a Register
Figure 18. Single Byte Read from a Register
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Read Word
In this operation, the master device receives two data bytes from a slave device as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserted ACK on SDA. 6. The master sends a repeated start condition on SDA. 7. The master sends the 7 bit slave address followed by the read bit (high) 8. The slave asserts ACK on SDA. 9. The slave sends the first Data Byte (low Data Byte). 10. The master asserts ACK on SDA. 11. The slave sends the second Data Byte (high Data Byte). 12. The masters asserts a No ACK on SDA. 13. The master asserts a stop condition on SDA and the transaction ends.
1 S 2 3 4 COMMAND CODE 5 6 7 8 9 10 SLAVE WA ADDRESS AS SLAVE DATA RA A ADDRESS (LSB) 11 12 13
5. The master sends the 7-bit slave address followed by the read bit (high). 6. The slave asserts ACK on SDA. 7. The slave sends the byte count N. 8. The master asserts ACK on SDA. 9. The slave sends the first data byte. 10. The master asserts ACK on SDA. 11. The slave sends the remainder of the data byes, the master asserts an ACK on SDA after each data byte. 12. After the last data byte the master asserts a No ACK on SDA. 13. The master asserts a STOP condition on SDA.
1 2 3 4 5 6 7 SLAVE SLAVE BYTE COUNT S WAS RA ADDRESS ADDRESS =N 8 A 9 DATA BYTE 1 10 A
...
...
11 DATA BYTE N
12 13 AP
Figure 20. Block Write to a Command Coder PMBus Timeout
DATA AP (MSB)
Figure 19. Word Read from a Command Code Block Read
In this operation, the master device sends a command byte, the slave sends a byte count followed by the stated number of data bytes to the master device as follows: 1. The master device asserts a START condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a REPEATED START condition on SDA.
Table 10. VR11.1 and VR11 x VID CODES for the NCP4200
OUTPUT OFF OFF 1.60000 1.59375 1.58750 1.58125 1.57500 1.56875 1.56250 VID7 0 0 0 0 0 0 0 0 0 VID6 0 0 0 0 0 0 0 0 0 VID5 0 0 0 0 0 0 0 0 0
The NCP4200 includes a PMBus timeout feature. If there is no PMBus activity for 35 ms, the NCP4200 assumes that the bus is locked and releases the bus. This prevents the device from locking or holding the PMBus expecting data. Some PMBus controllers cannot handle the PMBus timeout feature, so it can be disabled. Configuration Register 1 (0xD1) Bit 3 SMB_TO_EN = 1; PMBus timeout enabled. Bit 3 TODIS = 0; PMBus timeout disabled (default).
Virus Protection
To prevent rogue programs or viruses from accessing critical NCP4200 register settings, the lock bit can be set. Setting Bit 0 of the Lock/Reset sets the lock bit and locks critical registers. In this mode, certain registers can no longer be written to until the NCP4200 is powered down and powered up again. For more information on which registers are locked see the Register Map.
VID4 0 0 0 0 0 0 0 0 0
VID3 0 0 0 0 0 0 0 0 1
VID2 0 0 0 0 1 1 1 1 0
VID1 0 0 1 1 0 0 1 1 0
VID0 0 1 0 1 0 1 0 1 0
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NCP4200
Table 10. VR11.1 and VR11 x VID CODES for the NCP4200
OUTPUT 1.55625 1.55000 1.54375 1.53750 1.53125 1.52500 1.51875 1.51250 1.50625 1.50000 1.49375 1.48750 1.48125 1.47500 1.46875 1.46250 1.45625 1.45000 1.44375 1.43750 1.43125 1.42500 1.41875 1.41250 1.40625 1.40000 1.39375 1.38750 1.38125 1.37500 1.36875 1.36250 1.35625 1.35000 1.34375 1.33750 1.33125 1.32500 1.31875 1.31250 1.30625 1.30000 1.29375 VID7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 VID3 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 VID2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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NCP4200
Table 10. VR11.1 and VR11 x VID CODES for the NCP4200
OUTPUT 1.28750 1.28125 1.27500 1.26875 1.26250 1.25625 1.25000 1.24375 1.23750 1.23125 1.22500 1.21875 1.21250 1.20625 1.20000 1.19375 1.18750 1.18125 1.17500 1.16875 1.16250 1.15625 1.15000 1.14375 1.13750 1.13125 1.12500 1.11875 1.11250 1.10625 1.10000 1.09375 1.08750 1.08125 1.07500 1.06875 1.06250 1.05625 1.05000 1.04375 1.03750 1.03125 1.02500 VID7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID6 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
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NCP4200
Table 10. VR11.1 and VR11 x VID CODES for the NCP4200
OUTPUT 1.01875 1.01250 1.00625 1.00000 0.99375 0.98750 0.98125 0.97500 0.96875 0.96250 0.95625 0.95000 0.94375 0.93750 0.93125 0.92500 0.91875 0.91250 0.90625 0.90000 0.89375 0.88750 0.88125 0.87500 0.86875 0.86250 0.85625 0.85000 0.84375 0.83750 0.83125 0.82500 0.81875 0.81250 0.80625 0.80000 0.79375 0.78750 0.78125 0.77500 0.76875 0.76250 0.75625 VID7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 VID5 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 VID4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 VID3 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 VID2 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 VID1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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NCP4200
Table 10. VR11.1 and VR11 x VID CODES for the NCP4200
OUTPUT 0.75000 0.74375 0.73750 0.73125 0.72500 0.71875 0.71250 0.70625 0.70000 0.69375 0.68750 0.68125 0.67500 0.66875 0.66250 0.65625 0.65000 0.64375 0.63750 0.63125 0.62500 0.61875 0.61250 0.60625 0.60000 0.59375 0.58750 0.58125 0.57500 0.56875 0.56250 0.55625 0.55000 0.54375 0.53750 0.53125 0.52500 0.51875 0.51250 0.50625 0.50000 OFF OFF VID7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 VID3 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 VID2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1
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NCP4200
Table 11. PMBus Commands for the NCP4200
Cmd Code 0x01 R/W R/W Default 0x80 Description Operation # Bytes 1 Comment 00xx xxxx - Immediate Off 01xx xxxx - Soft Off 1000 xxxx - On (slew rate set by soft-start) - Default 1001 10xx - Margin Low (Act on Fault) 1010 10xx - Margin High (Act on Fault) Configures how the controller is turned on and off. Bit 7:5 4 Default 000 1 Comment Reserved for Future Use This bit is read only. Switching starts when commanded by the Control Pin and the Operation Command, as set in Bits 3:0. 0: Unit ignores OPERATION commands over the PMBus 1: Unit responds to OPERATION command, powerup may also depend upon Control input, as described in Bit 2 0: Unit ignores EN pin 1: Unit responds EN pin, powerup may also depend upon the Operation Register, as described for Bit 3 Control Pin polarity 0 = Active Low 1 = Active High This bit is read only. 1: means that when the controller is disabled it will either immediately turn off or soft off (as set in the Operation Command)
0x02
R/W
0x17
ON_OFF_Config
1
3
0
2
1
1
1
0
1
0x03
W
NA
Clear_Faults
0
Writing any value to this command code will clear all Status Bits immediately. The SMBus ALERT is deasserted on this command. If the fault is still present the fault bit shall immediately be asserted again. The Write_Protect command is used to control writing to the PMBus device. There is also a lock bit in the Manufacture Specific Registers that once set will disable writes to all commands until the power to the NCP4200 is cycled. Data Byte 1000 0000 0100 0000 0010 0000 Comment Disables all writes except to the Write_Protect Command Disables all writes except to the Write_Protect and Operation Commands Disables all writes except to the Write_Protect, Operation, ON_OFF_Config and VOUT_COMMAND Commands Enables writes to all commands Disables all writes except to WRITE_PROTECT, PAGE and all MFR-SPECIFIC Commands
0x10
R/W
0x00
Write Protect
1
0000 0000 0001 0000
0x19
R
0xB0
Capability
1
This command allows the host to get some information on the PMBus device. Bit 7 6:5 4 3:0 Default 1 01 1 000 Comment PEC (Packet Error Checking is supported) Max supported bus speed is 400 kHz NCP4200 has an SMBus ALERT pin and ARA is supported Reserved for future use
0x20 0x21 0x25
R R/W R/W
0x20 0x00 0x0020
VOUT_MODE VOUT_COMMAND VOUT_MARGIN_HIGH
1 2 2
The NCP4200 supports VID mode for programming the output voltage. Sets the output voltage using VID. Sets the output voltage when operation command is set to Margin High. Programmed in VID Mode.
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NCP4200
Cmd Code 0x26 0x38 0x39 0x4A R/W R/W R/W R/W R/W Default 0x00B2 0x0001 0x0000 0x0064 Description VOUT_MARGIN_LOW IOUT_CAL_GAIN IOUT_CAL_OFFSET IOUT_OC_WARN_LIMIT # Bytes 2 2 2 2 Comment Sets the output voltage when operation command is set to Margin Low. Programmed in VID Mode. Sets the ratio of voltage sensed to current output. Scale is Linear and is expressed in 1/W This offset is used to null out any offsets in the output current sensing circuitry. Units are Amps This sets the high current limit. Once this limit is exceeded IOUT_OC_WARN_LIMIT bit is set in the Status_IOUT register and an ALERT is generated. This limit is set in Amps. This sets the output power over power fault limit. Once exceeded Bit 1 of the Status IOUT Command gets set and the FAULT output gets asserted (if not masked). This sets the output power over power warn limit. Once exceeded Bit 0 of the Status IOUT Command gets set and the ALERT output gets asserted (if not masked) Bit 7 6 5 4 3 2 1 0 0x79 R 0x0000 STATUS WORD 2
Byte
0x68
R/W
0x012C
POUT_OP_FAULT_LIMIT
2
0x6A
R/W
0x012C
POUT_OP_WARN LIMIT STATUS BYTE
2
0x78
R
0x00
1
Name BUSY OFF VOUT_OV IOUT_OC Res Res CML None of the Above Bit 7 6 5 4
Description A fault was declared because the NCP4200 was busy and unable to respond. This bit is set whenever the NCP4200 is not switching. This bit gets set whenever the NCP4200 goes into OVP mode. This bit gets set whenever the NCP4200 latches off due to an overcurrent event.
A Communications, memory or logic fault has occurred. A fault has occurred which is not one of the above. Name Res OFF VOUT_OV IOUT_OC This bit is set whenever the NCP4200 is not switching. This bit gets set whenever the NCP4200 goes into OVP mode. This bit gets set whenever the NCP4200 latches off due to an overcurrent event. Description
Low Low Low Low
Low Low Low High High
3 2 1 0 7
Res Res CML None of the Above VOUT A Communications, memory or logic fault has occurred. A fault has occurred which is not one of the above. This bit gets set whenever the measured output voltage goes outside its power good limits or an OVP event has taken place, i.e. any bit in Status VOUT is set. This bit gets set whenever the measured output current or power exceeds its warning limit or goes into OCP. i.e. any bit in Status IOUT is set. A manufacturer specific warning or fault has occurred.
High
6
IOUT/POUT
High High
5 4
Res MFR
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NCP4200
Cmd Code R/W Default Description # Bytes High 3 Comment POWER_ GOOD Res OTHER Res Description This bit gets set whenever OVP event takes place. A Status bit in Status Other is asserted. The Power-Good signal is deasserted. Same as Power-Good in General Status.
High High High 0x7A R 0x00 STATUS VOUT 1 Bit 7
2 1 0 Name VOUT_ OVER VOLTAGE FAULT VOUT_ OVER VOLTAGE WARNING VOUT_ UNDER VOLTAGE WARNING VOUT_ UNDER VOLTAGE FAULT Res Res Res Res Name IOUT Overcurrent Fault Res IOUT Overcurrent Warning Res Res Res POUT Over Power Warning POUT Over Power Warning Fault Desc Supported Supported Supported Not supported Not supported Not supported Supported Not supported
6
This bit gets set whenever the measured output voltage goes above its power-good limit.
5
This bit gets set whenever the measured output voltage goes below its power-good limit.
4
Not applicable.
3 2 1 0 0x7B R 0x00 STATUS IOUT 1 Bit 7
Description This bit gets set if the NCP4200 latches off due to an OCP Event.
6 5
This bit gets set if IOUT exceeds its programmed high warning limit.
4 3 2 1
This bit gets set if the measured POUT exceeds the FAULT Limit. This bit gets set if the measured POUT exceeds the Warn Limit.
0
0x7E
R
0x00
STATUS CML
1
Bit 7 6 5 4 3 2 1 0
Name Invalid or Unsupported Command Received. Invalid or Unsupported Data Received. PEC Failed. Memory Fault Detected. Processor Fault Detected.
A communication fault other than the ones listed has occurred. Other memory or Logic Fault has occurred.
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NCP4200
Cmd Code 0x80 R/W R Default 0x00 Description STATUS_ALERT # Bytes 1 Bit 7 6 5 4 3 2 1 0 0x88 0x8B 0x8C 0x8D 0x96 0x99 0x9A 0x9B R R R R R R R R 0x00 0x00 0x00 0x00 0x00 0x4101 0x0002 0x0301 READ_POUT MFR_ID MFR_MODEL MFR_REVISION READ_VOUT READ_IOUT 2 2 2 2 2 1 2 1 Read-back Output Power, read back in Linear Mode in W's. 0x4101 0x0002 0x0301 Read-back output voltage. Voltage is read back in VID Mode. Read-back output current. Current is read back in Linear Mode (Amps). Name Res Res Res Res Res VMON WARN VMON FAULT Res Gets asserted when VMON exceeds it programmed WARN limits. Gets asserted when VMON exceeds it programmed FAULT limits. Comment Description
Table 12. Manufacturer Specific Command Codes for the NCP4200
Cmd Code 0xDO R/W R/W Default 0x00 Description Lock/Reset # Bytes 1 Bit 1 0 Name Reset Lock Comment Description Resets all registers to their POR Value. Has no effect if Lock bit is set. Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers become read-only and cannot be modified until the NCP4200 is powered down and powered up again. This prevents rogue programs such as viruses from modifying critical system limit settings. (Lockable). Description These bits sets the number of phases turned on during PSI. 00 = CL set for 1 Phase (default) 01 = CL set for 2 Phases 10 = CL set for 1 Phase 11 = CL set for 1 Phase
0xD1
R/W
0x07
Mfr Config
1
Bit 7:6
Name PSI
5 4 3
Res Res PMB_TO_EN PMBus Timeout Enable. When the PMB_TO_EN bit is set to 1, the PMBus Timeout feature is enabled. In this state if, at any point during an PMBus transaction involving the NCP4200, activity ceases for more than 35 ms, the NCP4200 assumes the bus is locked and releases the bus. This allows the NCP4200 to be used with SMBus controllers that cannot handle SMBus timeouts. (Lockable). Enable the FAULT pin, Default = 1. Enable the ALERT pin. When the ENABLE_MONITOR bit is set to 1, the NCP4200 starts conversions with the ADC and monitors the voltages.
2 1 0
FAULT_EN ALERT_EN ENABLE_ MONITOR
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NCP4200
Cmd Code 0xD2 R/W R/W Default 0x52 Description VR Config. 1A # Bytes 1 Bit 6:4 Name Phase Enable Bits 000 = Phase 1 100 = Phase 2 010 = Phase 3 110 = Phase 4 When the VID_EN bit is set to 1, the VID code in the VOUT_COMMAND register sets the output voltage. When VID_EN is set to 0, the output voltage follows the VID input pins. When the LOOP_EN bit is set to 1 in both registers, the control loop test function is enabled. This allows measurement of the control loop AC gain and phase response with appropriate instrumentation. The control loop signal insertion pin is IMON. The control loop output pin is COMP. When CLIM_EN is set to 1, the current limit time out latchoff functions normally. When this bit is set to 0 in both registers, the current limit latchoff is disabled. In this state, the part can be in current limit indefinitely. Comment Description
3
VID_EN
2
LOOP_EN
1
CLIM_EN
0 0xD3 R/W 0x52 VR Config. 1B 1
Res
This register is for security reasons. It has the same format as register 0xD2. Bits need to be set in both registers for the function to take effect. This resister sets TD1, TD3 and TD5 delays for the soft-start sequence. The current limit latchoff timer is 4 times the programmed delay time: 000 = 0.5 ms 001 = 1 ms 010 = 1.5 ms 011 = 2 ms = default 100 = 2.5 ms 101 = 3 ms 110 = 3.5 ms 111 = 4 ms This register sets the soft-start voltage slew rate, and hence TD2 and TD4, of the soft-start sequence: 000 = 0.1 V/ms 001 = 0.3 V/ms 010 = 0.5 V/ms = default 011 = 0.7 V/ms 100 = 0.9 V/ms 101 = 1.1 V/ms 110 = 1.3 V/ms 111 = 1.5 V/ms This register sets the slew rate during dynamic VID. This is a 16 bit value that reports back the voltage on the VTT Pin. Voltage is reported using Linear Mode. This is a 16 bit value that reports back the voltage measured between FB and FBRTN. Voltage is reported using Linear Mode. Offset Command Code for VOUT, max 200 mV. Offset Command Code for VOUT, max 200 mV. This value sets the internal load-line attenuation DAC calibration value. The maximum load-line is controlled externally by setting the gain of the current sense amplifier as explained in the applications section. This maximum load-line can then be adjusted from 100% to 0% in 30 steps. Each LSB represents a 3.226% change in the load-line. 00000 = No load-line 10000 = 51.6% of external load-line 11111 = 100% of external load-line
0xD4
R/W
0x03
Ton Delay
1
0xD5
R/W
0x02
Ton Rise
1
0xD6 0xD8 0xDA 0xDB 0xDC 0xDE
R/W R R R/W R/W R/W
0x01 0x00 0x00 0x00 0x00 0x10
Ton Transition EN/VTT Voltage VMON Voltage VOUT_TRIM VOUT_CAL Load-line Calibration
1 2 1 1 1 1
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NCP4200
Cmd Code 0xDF R/W R/W Default 0x00 Description Load-line Set # Bytes 1 Comment This value sets the internal load-line attenuation DAC value. The maximum load-line is controlled externally by setting the gain of the current sense amplifier as explained in the applications section. This maximum load-line can then be adjusted from 100% to 0% in 30 steps. Each LSB represents a 3.226% change in the load-line. 00000 = No load-line 10000 = 51.613% of external load-line 11111 = 100% of external load-line This value sets the PWRGD Hi Threshold and the CROWBAR Threshold: Code = 00, PWRGD HI = 300 mV (default) Code = 01, PWRGD HI = 250 mV Code = 10, PWRGD HI = 200 mV Code = 11, PWRGD HI = 150 mV This value sets the PWRGD Lo Threshold: Code = 000, PWRGD Lo = -500 mV (default) Code = 001, PWRGD Lo = -450 mV Code = 010, PWRGD Lo = -400 mV Code = 011, PWRGD Lo = -350 mV Code = 100, PWRGD Lo = -300 mV Code = 101, PWRGD Lo = -250 mV Code = 110, PWRGD Lo = -200 mV Code = 111, PWRGD Lo = -150 mV This value sets the internal current limit adjustment value. The default current limit is programmed using a resistor to ground on the LIMIT pin. The value of this register adjusts this value by a percentage between 50% and 146.7%. Each LSB represents a 3.33% change in the current limit threshold. 11111 = 146.7% of external current limit 10000 = 100% of external current limit (default) 00000 = 50% of external current limit These values adjust the gain of the internal phase balance amplifiers. The nominal gain is set to 5. These registers can adjust the gain by 25% from 3.75 to 6.25. Code = 00000, Gain of 3.75 Code = 10000, Gain of 5 (default) Code = 11111, Gain of 6.25 These values adjust the gain of the internal phase balance amplifiers. The nominal gain is set to 5. These registers can adjust the gain by 25% from 3.75 to 6.25. Code = 00000, Gain of 3.75 Code = 10000, Gain of 5 (default) Code = 11111, Gain of 6.25 These values adjust the gain of the internal phase balance amplifiers. The nominal gain is set to 5. These registers can adjust the gain by 25% from 3.75 to 6.25. Code = 00000, Gain of 3.75 Code = 10000, Gain of 5 (default) Code = 11111, Gain of 6.25 These values adjust the gain of the internal phase balance amplifiers. The nominal gain is set to 5. These registers can adjust the gain by 25% from 3.75 to 6.25. Code = 00000, Gain of 3.75 Code = 10000, Gain of 5 (default) Code = 11111, Gain of 6.25 VMON FAULT Limit VMON Warn Limit Bit 7 6 5 4 Name Mask VOUT Mask IOUT Res Res Description Masks any ALERT caused by bits in Status VOUT Register. Masks any ALERT caused by bits in Status IOUT Register.
0xE0
R/W
0x00
PWRGD Hi Threshold
1
0xE1
R/W
0x00
PWRGD Lo Threshold
1
0xE2
R/W
0x10
Current Limit Threshold
1
0xE3
R/W
0x10
Phase Bal SW1
1
0xE4
R/W
0x10
Phase Bal SW2
1
0xE5
R/W
0x10
Phase Bal SW3
1
0xE6
R/W
0x10
Phase Bal SW4
1
0xF5 0xF6 0xF9
R/W R/W R/W
0x0002 0x0002 0x00
VMON FAULT Limit VMON Warn Limit Mask ALERT
2 2 1
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NCP4200
Cmd Code R/W Default Description # Bytes 3 2 1 0 0xFA R/W 0x00 Mask FAULT 1 Bit 7 6 5 4 3 2 1 0 0xFB R 0x00 General Status 1 Bit 7 6 5 4 0xFC R 0x00 Phase Status 1 Bit 5 4 3 2 Mask CML VMON Res Mask POUT Name Mask VOUT Mask IOUT Res Res Mask CML VMON Res Mask POUT Name FAULT ALERT POWER_ GOOD RDY Name Phase 4 Phase 3 Phase 2 PSI Description This bit is set to 1 when Phase 4 is enabled. This bit is set to 1 when Phase 3 is enabled. This bit is set to 1 when Phase 2 is enabled. This bit is set to 1 when PSI is asserted. Replaced by Bit 3 of the Status Word Command Masks any FAULT caused by POUT exceeding its programmed limit. Description Masks any FAULT caused by bits in Status CML Register. Masks any ALERT caused by VMON exceeding its high or low limit. Masks any ALERT caused by POUT exceeding its programmed limit. Description Masks any FAULT caused by bits in Status VOUT Register. Masks any FAULT caused by bits in Status IOUT Register. Comment Masks any ALERT caused by bits in Status CML Register. Masks any ALERT caused by VMON exceeding its high or low limit.
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NCP4200
PACKAGE DIMENSIONS
QFN40 6x6, 0.5P CASE 488AR-01 ISSUE A
D AB
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30mm FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e L K MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 6.00 BSC 4.00 4.20 6.00 BSC 4.00 4.20 0.50 BSC 0.30 0.50 0.20 ---
2X
0.15 C
2X
0.15 C 0.10 C
40X
0.08 C
L
40X 10 EXPOSED PAD 11
b 0.10 C A B
40X
0.05 C
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
EEE EEE EEE
TOP VIEW (A3) SIDE VIEW A1 D2
20 21 1 40 31 30
PIN ONE LOCATION
E
A C K
SEATING PLANE
40X
SOLDERING FOOTPRINT*
6.30 4.20
40X
E2
0.65 1
e BOTTOM VIEW
36X
4.20 6.30
0.30
40X
0.50 PITCH
DIMENSIONS: MILLIMETERS
36X
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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32
NCP4200/D

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